verilog HDLBits刷题[Latches and Flip-Flops]“Edgedetect”---Detect an edge（边沿检测）

一、题目

For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.

Here are some examples. For clarity, in[1] and pedge[1] are shown separately.

Module Declaration

module top_module ( input clk, input [7:0] in, output [7:0] pedge );

二、分析

输入的某一位从0变为1时，对应一个上升沿。可先对输入进行打一拍，相当于将数据向右移动一个时钟周期；当移动前为1，移动后为0可判断数据在某个时钟延出现上升沿。画出每个变量的时序便可理解。

三、代码实现

注意：！的结果是一位，~是按位取反

module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; wire [7:0]pedge_temp; always@(posedge clk) in_1<=in; assign pedge_temp=in&(~in_1); always@(posedge clk) pedge<=pedge_temp; endmodule

module top_module ( input clk, input [7:0] in, output [7:0] pedge ); reg [7:0]in_1; always@(posedge clk) in_1<=in; integer i; always@(posedge clk) for(i=0;i<8;i=i+1) if(in[i]&(~in_1[i])) pedge[i]<=1; else pedge[i]<=0; endmodule 或者 module top_module ( input clk, input [7:0] in, output [7:0] pedge ); wire [7:0]in_1; always@(posedge clk)begin in_1<=in; end always@(posedge clk)begin for(int i=0;i<=7;i++)begin if ((in[i]==1'b1)&(in_1[i]==1'b0)) pedge[i]<=1'b1; else pedge[i]<=1'b0; end end endmodule

四、时序