一、题目
Design a 1-12 counter with the following inputs and outputs:
- ResetSynchronous active-high reset that forces the counter to 1
- EnableSet high for the counter to run
- ClkPositive edge-triggered clock input
- Q[3:0]The output of the counter
- c_enable, c_load, c_d[3:0]Control signals going to the provided 4-bit counter, so correct operation can be verified.
You have the following components available:
- the 4-bit binary counter (count4) below, which has Enable and synchronous parallel-load inputs (load has higher priority than enable). Thecount4module is provided to you. Instantiate it in your circuit.
- logic gates
module count4( input clk, input enable, input load, input [3:0] d, output reg [3:0] Q );Thec_enable,c_load, andc_doutputs are the signals that go to the internal counter'senable,load, anddinputs, respectively. Their purpose is to allow these signals to be checked for correctness.
Module Declaration
module top_module ( input clk, input reset, input enable, output [3:0] Q, output c_enable, output c_load, output [3:0] c_d );
二、分析
不是很理解其实
子模块的例化可以根据子模块的端口命名确定。
- Q[3:0]The output of the counter。即在子模块作为计数器输出。
- c_enable作为内部寄存器的使能，直接与顶层模块的使能相连。
- 要处理的只有三个信号：c_enable, c_load, c_d[3:0]。
三、 代码实现
module top_module ( input clk, input reset, input enable, output reg[3:0] Q, output c_enable, output c_load, output [3:0] c_d ); // assign c_enable=enable; always@(*) if(reset)begin c_load<=1'b1; c_d<=4'd1; end else if(enable == 1'b1 && Q == 4'd12)begin c_load<=1'b1; c_d<=4'd1; end else begin c_load<=1'b0; c_d<=4'd0; end count4 the_counter (.clk(clk), .enable(enable), .load(c_load), .d(c_d) ,.Q(Q) ); endmodule 或者 module top_module ( input clk, input reset, input enable, output [3:0] Q, output c_enable, output c_load, output [3:0] c_d ); // count4 the_counter (clk, c_enable, c_load, c_d,Q ); assign c_enable=enable; assign c_load=reset|(enable& Q==4'd12); assign c_d=1; endmodule四、时序
